Silicon Power Efficiency Design Engineer, Machine Learning Accelerators Full-time

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
• Experience with silicon power reduction techniques
• Experience in Register Transfer Level (RTL) logic design using SystemVerilog or similar Hardware Description Language (HDL), and industry experience in silicon power or RTL design.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 15 years of experience in ASIC design.
• Experience in developing chip power architecture or design. Experience with optimizing silicon designs for low-power
• Experience in data center power profiling and reducing carbon footprint.
• Experience in pre-silicon power modeling and measurement.
• Understanding techniques such as Dynamic and Voltage and Frequency Scaling (DVFS), Turboing, Thermal management and Firmware based power management techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

You will be part of a silicon design team developing ASICs used to accelerate machine learning computation in data centers. With a focus on power architecture and design, you will have dynamic, multi-faceted responsibilities across architecture, design and implementation. Your contributions will help shape future generations of data center Machine Learning accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $177,000-$266,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Contribute to the development and successful delivery of complex silicon systems.
• Create and maintain policies, processes, procedures, methods, tests, and documentation of silicon deliverables for the purpose of enhancing and promoting high efficiency, productivity, and sustainability.
• Identify test requirements, select appropriate tools, methods, and approach, and carry out testing of Silicon systems, influence designs to enable and enhance testing, validation, and debugging.