Silicon AI/ML IP Design Lead, Google Cloud Full-time

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 15 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.
• Experience in micro-architecture and design of Graphics or Machine Learning IPs, managing Low Precision/Mixed Precision Numerics.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Experience with scripting languages (e.g., Python or Perl).
• Experience in SoC designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high performance and low power design techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Lead a team of engineers in the Bengaluru design organization to deliver compute intensive IPs and subsystems.
• Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
• Take ownership of one or more complex IPs or subsystems and implement RTL.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
• Identify and drive power, performance, and area improvements for the domains owned.