PHY Design IP Integration Technologist, Machine Learning, PhD, University Full-time

Minimum qualifications:

• PhD degree in Electrical Engineering, Computer Science, or equivalent practical experience
• Academic, educational, internship or project experience designing or integrating analog PHY designs (e.g., PCIe, UCIe, or HBM PHYs)
• Academic, educational, internship or project experience with design integration flows and requirements

Preferred qualifications:

• Experience coordinating designs through the entire silicon product lifecycle
• Experience writing design specifications
• Experience sourcing IPs from third-party vendors
• Expertise in one or more of the following standards: PCIe, UCIe, HBM, Ethernet

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the TPU interface design team, you will play a pivotal role in pushing the boundaries of technology to improve the performance and power of our TPUs. You will drive the selection, integration, and execution of our high speed IO Design IPs. In this highly cross-functional role, you will be tasked with specifying and meeting the technical requirements and coordinating all aspects of the IP integration across all phases of the silicon lifecycle.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Contribute to PHY Design IP selection and procurement process.
• Own PHY Design IP planning and roadmap definition.
• Drive pre-silicon integration of PHY Design IPs.
• Coordinate PHY Design IP requirements with cross-functional teams (e.g., Design, Verification, Physical Design, DFT, Post-Silicon).
• Assist in post silicon bring-up and validation of PHY IP designs.