Design Verification Lead, AI/ML, Google Cloud TPU Full-time

Minimum qualifications:

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 16 years of experience with functional verification and performance validation of modern mobile processors, microarchitecture, and related technologies.
• Experience leading a functional verification team delivering IPs, SoC and Subsystems.
• Experience in development of verification environment using UVM/SystemVerilog.

Preferred qualifications:

• Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
• Experience scripting using Python, Perl, or Shell scripts.
• Experience leading and managing complex verification projects.
• Understanding of ARM instruction set architecture.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will collaborate with Design, Performance, and Architecture teams, and work to ensure delivery of production-quality IPs and SoCs. The infrastructure will include unit, multi-unit, core, and subsystem-level verification environments.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Develop and drive the overall verification strategy and plan for SoC projects. Define verification methodologies, environments, and test plans at both block, IP, Subsystem and chip level. Identify and evaluate new verification tools and methodologies to improve efficiency and effectiveness.
• Architect and develop reusable testbench components and environments using advanced verification languages (SystemVerilog, UVM). Guide the development of directed and constrained-random test cases to achieve comprehensive functional coverage. Oversee the execution of simulations, debug failures, and analyze coverage data.
• Collaborate with Design, Architecture, and Software teams to understand design requirements and ensure alignment with verification goals. Provide technical guidance and mentorship to junior verification engineers. Lead reviews of verification plans, testbenches, and coverage reports.
• Contribute to the development, refinement of company-wide verification methodologies, flows. Research and evaluate emerging verification technologies and trends.