ASIC Design Lead, Machine Learning, Silicon Full-time

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 10 years of experience in RTL design.
• Experience leading a team completing the full development cycle of SoC subsystems (e.g., Neural Processing Units, GPU, DSP, or processors, from conception to production).
• Experience working cross-functionally with Software, Architecture, Design Verification, and SoC integration teams.

Preferred qualifications:

• Master’s degree or PhD in Computer Science, Electrical Engineering, or a related field.
• Experience in engineering across architecture, micro-architecture, design verification, implementation, emulation, and silicon bring-up.
• Experience with high performance compute IPs (e.g., GPUs, DSPs, or Neural Processing Units).

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user’s interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people’s lives better through technology.

Responsibilities

• Manage a team of RTL engineers, plan and lead the design of complex machine learning compute IPs by fully understanding the architecture specification, and interact with software and architecture engineers to identify important design requirements.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and physical design of digital blocks.
• Participate, guide, and motivate the team for timely execution and exceptional Power Performance Area (PPA) benchmarks for these IPs that will go into a wide range of SoCs.
• Work with SoC Design and other cross-functional implementation teams to make sure the IP design is successfully implemented through the downstream domains all the way to tape-out.